Jiahang Lou 楼佳杭
About
I am a Ph.D. student in Electronics Engineering (EE) at the State Key Laboratory of Integrated Circuits and System, Fudan University, supervised by Prof. Lingli Wang. My research focuses on reconfigurable architectures (e.g. CGRAs) and AI compiler design, with a particular emphasis on MLIR-based compilation frameworks, tensor dataflow optimization, and heterogeneous CGRA–CPU systems for AI workloads.
I have published as the first author at DATE 2024 and DAC 2025, and have participated in several national and international competitions related to electronic design and GPU programming.
- Research Interests:
- Coarse-Grained Reconfigurable Architectures (CGRAs)
- Compiler design and MLIR-based compilation frameworks
- AI deployment and dataflow-aware tensor optimization for DNNs
- Polyhedral model and loop transformations
- Heterogeneous accelerator–CPU systems and communication optimizations
Education
- Ph.D. in Electronics Engineering — Fudan University, Shanghai, China · Sept. 2022 – Jun. 2027 (expected)
- Supervisor: Prof. Lingli Wang (llwang@fudan.edu.cn)
- B.Sc. in Microelectronics — Fudan University, Shanghai, China · Sept. 2018 – Jun. 2022
Recent News
- Dec 2025 — 我们团队将在 FPT 2025（上海科技大学张江校区）举办Fusion SoC的tutoral-workshop，现场还开放了CGRA工具链的云端体验~link
- Dec 2025 — Co-hosting “Fusion SoC tutorial-workshop” at FPT 2025 (ShanghaiTech University) on Dec 2. Come play with our CGRA toolchain! See https://fpt-2025.lin.pub
- Nov 2025 — Shared a Chinese interpretation of the FPGA2025 best paper, FlightVGM: Video-Generation Model Deployed on FPGA, on Zhihu. Read more
- June 2025 — Scheduled to deliver an oral presentation at DAC 2025. See ya in San Francisco!
- Feb. 2025 — Our CGRA compiler work has been accepted by DAC 2025.
Selected Publications
- Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs — Jiahang Lou, et al.; Design Automation Conference (DAC), San Francisco, USA, June 21–25, 2025. Github: adora-compiler** A unified framework bridging user-friendly programming and high-performance acceleration for CGRAs through automated loop transformations, task/data-flow optimization, and systematic algorithms.
An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture — Jiahang Lou, et al.; Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, March 22–25, 2024. A user-friendly MLIR-based multi-level compiler framework that bridges CGRA and RISC-V CPU architectures by automating optimizations and hardware–software partitioning for large-scale workloads.
- View all publications
Competition Experiences - view details
Internship - view details
Awards - view details
Contact
- Email: jhlou22@m.fudan.edu.com
- Location: Zhangheng Road 825, Shanghai, China 张衡路825号,复旦大学,上海浦东新区
- GitHub: MIONkb
- Google Scholar: Jiahang Lou
Last updated: Dec. 26 , 2025.