Jiahang Lou (Mion)

Jiahang Lou (Mion)

Ph.D. candidate in EE at Fudan University focusing on reconfigurable computing and AI compiler

Jiahang Lou 楼佳杭

About

I am a Ph.D. student in Electronics Engineering (EE) at the State Key Laboratory of Integrated Circuits and System, Fudan University, supervised by Prof. Lingli Wang. My research focuses on reconfigurable architectures (e.g. CGRAs), AI compiler design and DNN/LLM Depolyment, with a particular emphasis on MLIR-based compilation frameworks, tensor dataflow optimization, and heterogeneous CGRA–CPU systems for AI workloads.

I have published papers at venues such as DATE 2024 and DAC 2025, and have participated in national and international competitions in electronic design and GPU programming. I also have internship experience at leading technology companies.

Research Interests:

  • Compiler
    • Compiler design and MLIR-based compilation frameworks
    • Polyhedral model and loop transformations
    • Dataflow-aware tensor optimization for DNNs
  • DNN/LLM Deployment
    • Heterogeneous accelerator–CPU systems and communication optimizations
    • LLM inference/training optimization on multi-GPU/NPU (parallelism, communication, scheduling)
  • Computing Architecture
    • Coarse-grained reconfigurable architectures (CGRAs)
    • Advanced computing architectures for LLMs and DNNs (e.g., NoC, Chiplet-based systems)

Education

  • Ph.D. in Electronics Engineering — Fudan University, Shanghai, China · Sept. 2022 – Jun. 2027 (expected)
  • B.Sc. in Microelectronics — Fudan University, Shanghai, China · Sept. 2018 – Jun. 2022

Recent News

  • May 2026 — We will give an on-site demo at ISCAS 2026 (Shanghai) of deploying CGRA on FPGA to support diverse workloads, including Llama inference—a small “continue-your-story” LLM deployment demo. Come and try our storytelling experience and the full toolchain in Shanghai! Special thanks to Jianrong for the close collaboration and huge contributions!
  • Mar 2026 — Our paper has been accepted by ISEDA 2026. Special thanks to Jiayao for the great collaboration!
  • Jan 2026 — Our work Live Demonstration: an Agile FPGA-Overlayed CGRA SoC for High-Efficiency Computing has been accepted by ISCAS 2026.
  • Jan 2026 — Joined ByteDance’s AI chip team as an intern, contributing to the software stack for LLM acceleration.
  • Dec 2025 — Co-hosting “Fusion SoC tutorial-workshop” at FPT 2025 (ShanghaiTech University) on Dec 2. Come play with our CGRA toolchain! See https://fpt-2025.lin.pub

Selected Publications

  • Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs — Jiahang Lou, et al.; Design Automation Conference (DAC), San Francisco, USA, June 21–25, 2025. Github: adora-compiler** A unified framework bridging user-friendly programming and high-performance acceleration for CGRAs through automated loop transformations, task/data-flow optimization, and systematic algorithms.

  • An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture — Jiahang Lou, et al.; Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, March 22–25, 2024. A user-friendly MLIR-based multi-level compiler framework that bridges CGRA and RISC-V CPU architectures by automating optimizations and hardware–software partitioning for large-scale workloads.

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Competition Experiences - view details

Internship - view details

Awards - view details

Contact

Last updated: Mar. 26 , 2026.