Jiahang Lou 楼佳杭

About

I am a Ph.D. student in Electronics Engineering (EE) at the State Key Laboratory of Integrated Circuits and System, Fudan University, supervised by Prof. Lingli Wang. My research focuses on reconfigurable architectures (e.g. CGRAs) and AI compiler design, with a particular emphasis on MLIR-based compilation frameworks, tensor dataflow optimization, and heterogeneous CGRA–CPU systems for AI workloads.

I have published papers at venues such as DATE 2024 and DAC 2025, and have participated in national and international competitions in electronic design and GPU programming. I also have internship experience at leading technology companies.

• Research Interests:
  • Coarse-Grained Reconfigurable Architectures (CGRAs)
  • Compiler design and MLIR-based compilation frameworks
  • LLM inference/training optimization on multi-GPU/NPU systems (parallelism, communication, scheduling)
  • AI deployment and dataflow-aware tensor optimization for DNNs
  • Polyhedral model and loop transformations
  • Heterogeneous accelerator–CPU systems and communication optimizations

Education

• Ph.D in Electronics Engineer, Fudan University, 2022 - 2027(expected)
  • supervisor: Prof. Lingli Wang
• B.S. in Micro-Electronics, Fudan University, 2018 - 2022

Open-Source Projects

• Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs. Design Automation Conference (DAC 2025).
  • GitHub: https://github.com/FDU-ME-ARC/adora-compiler
  • An MLIR-based unified framework that bridges user-friendly programming (C, PyTorch, ONNX) and high-performance CGRA acceleration through automated loop transformations, task/dataflow optimization, and systematic mapping.
  • Multiple frontend input types:
    • C via Polygeist
    • PyTorch via Torch-MLIR
    • ONNX via adora-onnx-mlir (an self-hosted ONNX-MLIR version for our ADORA)
  • Multi-level optimization:
    • For ONNX-based neural networks: dataflow optimization for GEMM; other operators are lowered to affine loop nests
    • For loop programs: polyhedral-based loop transformations (tiling, unrolling, reordering), plus branch and peephole optimizations
  • Multiple backends:
    • Rocket + CGRA in the Chipyard environment
    • Cocotb-based CGRA simulation
    • FPGA prototypes via Xilinx Vitis SDK
• “Vitra” Reconfigurable Array Design — a partitionable and dynamically reconfigurable CGRA architecture
  • GitHub: https://github.com/MIONkb/VITRA-CGRA
  • A CGRA design supporting partition-aware dynamic reconfiguration and flexible resource allocation
  • Implements AXI data path and AXI-Lite control path for host–CGRA communication with on-CGRA memory access
  • Includes a Cocotb-based simulation environment for cycle-accurate verification

Publications

• Live Demonstration: an Agile FPGA-Overlayed CGRA SoC for High-Efficiency Computing(Accepted). Jiahang Lou, Jianrong Zhang(Co-first), Yuan Dai, Zewei Zhong, Huan Lin, Wenbo Yin, Lingli Wang. 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026), Shanghai, China

• Co-Hosting Fusion SoC Tutorial-Workshop at FPT 2025. Hosted by Lingli Wang’s group, including Yuan Dai, Jiahang Lou, Jingyuan Li, Huan Lin, Guibin Zou, XinYu Cai and other team members. International Conference on Field Programmable Technology (FPT 2025-workshop), ShanghaiTech University, Shanghai — link

• Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAs. Jiahang Lou, Qilong Zhu, Yuan Dai, Zewei Zhong, Wenbo Yin and Lingli Wang. Design Automation Conference (DAC 2025), San Francisco, USA. paper

• MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes. Shaoyang Sun, Boyin Jin, Jiahang Lou, Jiangnan Li, Yuhang Cao, Jingyuan Li, Chen Shen, Yuan Dai, Wenbo Yin, Wai-Shing Luk, Lingli Wang. 35th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2024), Hong Kong, China. paper

• CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design. Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang. 34th International Conference on Field-Programmable Logic and Applications (FPL 2024), Torino, Italy. paper

• An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture. Jiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang. Design, Automation & Test in Europe Conference & Exhibition(DATE 2024), Valencia, Spain. paper

Competition

• 2024 Biren Technology “Flying Cup” GPU Programming Challenge — National First Place · 40,000 RMB · Jul. 2024 – Aug. 2024.
  • GPU-based development of AI operators(TopK, ReduceMean) with performance-optimized CUDA kernels and system-level integration.
  • 2024年壁仞科技“飞翔杯”GPU编程大赛 全国第一名 · 40000元。
  • link
• 2023 “Fudan Electronics Cup” National College Electronic Design Competition — National First Prize · 20,000 RMB · May 2023 – Aug. 2023.
  • MLIR-based compiler development for AI model quantization and deployment on embedded platforms.
  • 2023年复旦微全国大学生电子设计大赛 软硬件赛道 全国一等奖 · 20000元。
  • link
• The 5th National College IC Competition for Innovation and Entrepreneurship (CICC) — Second Prize of National Finals · 15,000 RMB · Mar. 2021 – Aug. 2021.
  • Led a team to develop a speech-controlled wireless smart helmet using a Xilinx FPGA and the IEEE 802.11ah protocol. Responsible for the hardware/software architecture, low-level hardware interfaces, Verilog-based speech recognition accelerator, RISC-V CPU integration, and SDK development.
  • 2021年第五届全国大学生集成电路创新创业大赛 国家级二等奖 · 15000元。

Intern Experience

• ByteDance, Shanghai — AI Silicon-AI Software Stack Intern· Jan. 2026 – Present.
  • Explore LLM-oriented accelerator architecture via simulation and profiling, focusing on compute/communication trade-offs and GPU/NPU workload groups for LLM training and inference.
• AMD (Advanced Micro Devices), Shanghai — GPU Post Silicon Intern – Semi-Custom Business Unit (SCBU)· Aug. 2021 – Jan. 2022
  • Developed Python-based tools and infrastructure for post-silicon validation and internal server platforms.
  • Built a runtime power monitor for key on-board nodes using STM32 and ADC chips.
• The 5th national College IC Competition for innovation and entrepreneurship (CICC) - Competition Technical Assistant·Feb. 2021 – Aug. 2021
  • One of the 17 technical assistants of the competition, responsible for the communication and coordination among the Alibaba T-head company, organizers of the contest and the participating teams, and answer technical questions for the contestants.
  • 第五届集创赛助理 获“优秀杯赛助理奖”

Skills

• Programming Language:
  • C/C++, CUDA, Verilog, Chisel(Scala), Python, Shell, Markdown
• Programming Framework:
  • Pytorch, Tensorflow, MLIR, LLVM, Matlab, CMAKE
• Software:
  • Vivado/Vitis, Keil, Synopsys Design-Compiler, VCS, Verilator, Git
• Language:
  • Chinese(native), English(CET6 IELTS6.5)
• Sports:
  • Basketball

Honors

• Graduate First-Class Scholarship of Fudan University (复旦大学研究生一等奖学金), 2023, 2024
• University-Level First-Class Scholarship (Huawei Scholarship) of Fudan University (复旦大学校级奖学金一等奖（华为奖学金）), 2021
• University-Level Second-Class Scholarship of Fudan University (复旦大学校级奖学金二等奖), 2020
• University-Level First-Class Scholarship (Guanghua Scholarship) of Fudan University (复旦大学校级奖学金一等奖（光华奖学金）), 2019
• Outstanding Graduate of Fudan University(复旦大学优秀毕业生), 2022
• Outstanding Student Award of Fudan University (复旦大学优秀学生), 2019
• Computer Software Copyright Registration (China), 1st student contributor (ID.2025SR2155561), 2025

Contact

• Email: jhlou22@m.fudan.edu.com
• Location: Zhangheng Road 825, Shanghai, China 张衡路825号,复旦大学张江校区,上海浦东新区
• Homepage: https://MIONkb.github.io
• GitHub: https://github.com/MIONkb