Jiahang Lou (Mion)

Jiahang Lou (Mion)

Ph.D. candidate in EE at Fudan University focusing on reconfigurable computing and AI compiler

An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture

Published in Design, Automation & Test in Europe Conference & Exhibition (DATE 2024), Valencia, Spain, 2024

A user-friendly MLIR-based multi-level compiler framework that bridges CGRA and RISC-V CPU architectures by automating optimizations and hardware–software partitioning for large-scale workloads.